| 摘要 |
PURPOSE:To eliminate the frequency fluctuation of a reference clock in the system operation of a digital signal input device by immediately switching the reference clock from the output of a PLL circuit to that of a crystal oscillator when the step out of PLL occurs when a digital signal is inputted. CONSTITUTION:This controller is equipped with a PLL circuit 4 which outputs the reference clock 1 for the system operation synchronized with DIN(digital input data) to record a digital input signal, a PLL synchronous detection circuit 15 which outputs a PLL synchronous detection signal, a selector 1(9) which outputs one reference clock 2 from N (N:integer >=1) crystal oscillators, and a selector 2(10), and when the step out of PLL occurs while an R-DAT is recording the digital input signal, the selector 2(10) immediately switches the reference clock of the R-DAT from the reference clock 1 from the PLL circuit 4 to the reference clock 2 that is the output of the crystal oscillator of the same FS as that of the DIN before the step out of PLL occurs by setting the PLL synchronous detection signal 1 at a high level by the PLL synchronous detection circuit 15. |
