DRAM with sync. data transfer - has data latching circuit responding to signal from address bridging detector unit

摘要

A memory cell matrix (27) has parallel bit lines (BL) and orthogonal, parallel bit lines (BL) and orthogonal, parallel, word lines (WL), the memory cells (MC) being arranged at their intersection points. An input/output buffer (30) between data lines (29,31) pref. comprises a complementary MOSFET differential amplifier. The second data lines (31) are coupled to a latch output circuit (32), with an equaliser (35) between them for resetting the data lines (31). Pref., the latter are arranged in at least two pairs, with a temporary buffer (34) between them. ADVANTAGE - High-speed data transfer.