DRAM with high-speed data access - uses booster circuit coupled to row decoder providing word line driver voltage

摘要

The memory has a row and column memory cell array (14) with word lines (WL) for addressing the different rows and bit lines (BL) for addressing the different columns. The word lines are coupled to a row decoder (20) and a core control circuit (24), the bit lines coupled to a column decoder (26) and a read amplifier (42). The address of each required memory cell is fed to row and column address buffers, in turn coupled to the row and column decoders, the row decoder coupled to a booster circuit (34) for providing the word line driver voltage (Vbw), fed to the core control circuit, before interrogation of the row address. ADVANTAGE - High packing density and high speed word line control technique.