| 摘要 |
<p>A data bus clamping circuit is adapted for use in a semiconductor memory device including a memory cell array (10) for storing data, a row address decoder(20) for decoding row address signals (XADm) taken in by a row address strobe signal (RAS) to select memory cells in a row direction of the memory cell array, a column address decoder (40) for decoding column address signals (YADn) based on a column address decoder enabling signal (YDE) to select memory cells in a column direction of the memory cell array, complementary data buses (DB and DB) for transmitting data read out from the memory cell array, a data bus pull-up circuit (50) for pulling up the complementary data buses, and a differential amplification type of readout circuit (70) for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit (100) for discharging electric charge on said complementary data buses during an active period of the row address strobe signal (RAS), and a second discharge circuit (110) for discharging electric charge on said complementary data buses with a discharge ability larger than said first discharge circuit 100, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active. <IMAGE></p> |
