| 摘要 |
<p>A semiconductor memory device comprises memory cells, bit line pairs, word lines for allowing data bits to be read out from a row of the memory cells to the bit line pairs, sense amplifier circuits for increasing the magnitudes of small differential voltage levels on the bit line pairs, and a transfer gate array responsive to a column selecting signal for interconnecting one of the bit line pairs and a data line pair, wherein a monitoring circuit monitors one of the bit line pairs to be whether or not the sense amplifier circuit sufficiently increases the magnitude for allowing the column selecting signal to reach the transfer gate array so that any error due to insufficient magnitude does not take place in a read-out operation. <IMAGE></p> |
