| 摘要 |
PURPOSE:To reduce the circuit scale by using a comparison timing pulse to compare held input data and read data with each other at the time when data corresponding to held input data is read out from a memory means. CONSTITUTION:Address data out of data written in a memory means 1 is held in a data holding and comparing means 5 by a holding timing pulse, and the comparison timing is used to detect coincidence/disaccord between read data and held data when address data is read out. Since an (N+1)-ary counter means 4 has a period one clock longer than that of an N-ary counter means 2, next address data in the memory means 1 is held in the data holding and comparing means 5 just after data comparison. That is, the address to be held and com pared is successively shifted by the (N+1)-clock period to diagnose all addresses. Thus, it is unnecessary to hold data of all addresses, and the circuit scale is reduced. |
