发明名称 CLOCK SIGNAL GENERATOR
摘要 PURPOSE:To generate a clock with a fast reply to a phase fluctuation by providing a phase modulation means receiving a phase of a clock outputted from a voltage controlled oscillator means and receiving an error signal outputted from a phase comparison means as a modulation input to the generator. CONSTITUTION:A clock outputted from a voltage controlled oscillator 53 is inputted to a phase modulator 56. Moreover, a phase error signal outputted from a phase comparator 51 is inputted to the phase modulator 56 after the gain is adjusted to a prescribed gain by a gain adjustment device 55. The phase modulator 56 applies phase modulation to the clock inputted from the voltage controlled oscillator 53 corresponding to a modulation signal inputted from the gain adjustment device 55. Thus, a phase error difficult to be fallowed by a PLL circuit is corrected by an open servo loop by the phase modulator 56 to decrease the phase error further more.
申请公布号 JPH03272222(A) 申请公布日期 1991.12.03
申请号 JP19900072927 申请日期 1990.03.20
申请人 VICTOR CO OF JAPAN LTD 发明人 KOSAKA YOSHITERU
分类号 H03L7/08;H03C3/00 主分类号 H03L7/08
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