发明名称 SHIFT BUS SELECTION CIRCUIT
摘要 PURPOSE:To store the shift-in data '0' into all buses in only the shift-in time set to a single bus by shifting simultaneously the data '0' into plural shift buses in number accordant with the longest bus. CONSTITUTION:When the data is shifted into a shift No '1' via a diagnostic device, a clock stop signal 500 is set at '1' to stop the clocks supplied to the FF 16 - 24. Then a shift instruction signal 200 is set at '1' and at the same time a shift bus selection signal 300 is set at '01'. Thus a signal line 31 is set at 1 and the clock signals 400 are supplied to only the FF 19 -21 forming a shift bus '1' through a signal line 120. The shift data given from the diagnostic device are shifted via a signal line 800. When the same value '0' is set to the FFs forming the shift buses '0', '1' and '2' respectively, the signal 500 is set at '1' and the clock signals 400 supplied to the FF 16 - 24 are stopped. Then '0' is applied to a signal line 800 and then successively shifted in.
申请公布号 JPH03269641(A) 申请公布日期 1991.12.02
申请号 JP19900070157 申请日期 1990.03.19
申请人 NEC CORP 发明人 AZUMA YOSHIYASU
分类号 G01R31/317;G06F11/22 主分类号 G01R31/317
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