| 摘要 |
PURPOSE:To form a frame synchronizing circuit independently of a gate delay time by inserting a flip-flop(FF) on the way of 1st and 2nd gate circuits so as to interrupt the accumulation of gate delay times. CONSTITUTION:An FF 30 is inserted between a NAND gate 15 detecting a frame synchronizing signal and a NAND gate 16 generating a signal inhibiting the input of a clock signal (CLK) to a 1/5 frequency divider circuit. Thus, a frame synchronizing signal detection signal is delayed by one bit, the accumulation of gate delay times at this point of time is once interrupted and the delay time is brought into zero. Thus, the gate delay in the output of the NAND gate 16 is added with only that resulting from the NAND gate 16 itself. Consequently, the rise of the NAND gate 16 does not interfere with the rise of the CLK. |
