发明名称 DOWN DETECTION SYSTEM FOR DISPLAY PROCESSOR
摘要 <p>PURPOSE:To reduce the overhead of a CPU by providing a flag between a CPU and a display processor and monitoring/controlling the flag at each prescribed time for detection of the down of the display processor. CONSTITUTION:The states of flags 121 and 122 of a flag part 12 are inputted to a CPU 10 and then to a flag control part 11. The flag 122 is set in an ON state when a command is given to a display processor 13 from the CPU 10. When an answer is sent back to the CPU 10 from the processor 13 against the command, both flags 121 and 122 of the part 12 are turned off. A control part 11 is started by a periodic signal and discriminate the state of the part 12. Then the part 11 produces the down display output of the processor 13 as long as both flags 121 and 122 are kept ON. If the flag 122 is kept OFF, the operation is through with nothing done. Meanwhile a drive signal is produced so that the flag 121 is turned on when the flags 122 and 121 are kept ON and OFF respectively.</p>
申请公布号 JPH03269642(A) 申请公布日期 1991.12.02
申请号 JP19900069443 申请日期 1990.03.19
申请人 FUJITSU LTD 发明人 TAKEUCHI AKIHIKO
分类号 G06F11/30;G06F3/048;G06F3/14;G09G5/00 主分类号 G06F11/30
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