发明名称 SIGNAL DETECTION CIRCUIT
摘要 PURPOSE:To increase the possibility of establishing phase locking sufficiently even in an input signal with a short consecution time by multiplying a signal frequency in an input signal consecutive time by a number of gradual multiple. CONSTITUTION:A frequency multiplier circuit 100 outputs an output signal S100 multiplying a frequency of an input signal S1 by a predetermined gradual multiple number N. A phase lock detection circuit 300 compares the output signal S100 of a frequency gradual multiple circuit 100 with a frequency signal S200 of a phase locked loop circuit 200 and the phase locked loop circuit 200 detects whether or not the state is in the phase lock establishing state to detect a frequency component of 1/N component included in the input signal S1. Thus, since the signal period number in an input signal consecutive time is multiplied by the number of gradual multiple, the possibility of establishing the phase lock sufficiently is increased even in the input signal with a short consecutive time and the signal detection capability of the signal detection circuit is considerably improved.
申请公布号 JPH03270592(A) 申请公布日期 1991.12.02
申请号 JP19900072304 申请日期 1990.03.20
申请人 FUJITSU LTD 发明人 SATO TOSHIYUKI
分类号 H03K5/19;H03B19/16;H03D3/24;H03L7/095;H04L27/00;H04M15/00;H04Q1/44;H04Q1/446 主分类号 H03K5/19
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