发明名称 VARIABLE LENGTH ENCODING CONTROL SYSTEM
摘要 PURPOSE:To improve the coding efficiency by implementing encoding with adaptive bit allocation corresponding to the sets of subblocks resulting from division and using the result of coding as a variable encoding output. CONSTITUTION:A dividing means 1 divides either or both of frequency and time, and the dividing means 1 divides the block of a prescribed length into subblocks. The division number in this case forms the sets of different subblocks and an encoding section 2 applies coding at every set by the allocation of an adaptive bit. An evaluation section 3 obtains an evaluation function based on the result of encoding at every set of subblocks and selects a set of subblocks with a best evaluation function, and when, e.g. quantization noise power is used as the evaluation function, a set of the subblocks minimizing the quantization noise power is selected. Thus, the variable length code is obtained based on optimum bit allocation according to the optimum division number of subblocks corresponding to the change in a signal power in the block. Thus, the encoding processing efficiency is improved.
申请公布号 JPH03270324(A) 申请公布日期 1991.12.02
申请号 JP19900068056 申请日期 1990.03.20
申请人 FUJITSU LTD 发明人 OKAZAKI KOJI;ISEDA HIDEHIRA;MATSUO NAOJI;UMIGAMI SHIGEYUKI
分类号 H04N19/00;H03M7/40;H04L25/49;H04N19/122;H04N19/13;H04N19/136;H04N19/146;H04N19/154;H04N19/176;H04N19/189;H04N19/196;H04N19/46;H04N19/59;H04N19/63;H04N19/70;H04N19/80;H04N19/85;H04N19/91 主分类号 H04N19/00
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