发明名称 OUTPUT BUFFER CIRCUIT
摘要 PURPOSE:To realize an output buffer circuit with low noise, at high speed capable of large current driving and to decrease the number of output transistors(TRs) by decreasing the ON resistance of the plural output TRs turned on sequentially in parallel with an output terminal more than the ON resistance of the output TRs turned on just before. CONSTITUTION:Plural output TRs 40-43 connected in parallel with an output terminal are provided and the output TRs 40-43 are sequentially turned on and a signal with an output level in response to the input signal is outputted from the output terminal in the output buffer circuit and the ON-resistance of the output TRs 40-43 is set smaller than the ON resistance of the output TRs turned on just precedingly. Thus, the number of output TRs connected in parallel is decreased to obtain sufficient high speed performance, noise at the switching is reduced and the distortion of waveform such as undershoot, overshoot or ringing due to signal reflection is reduced.
申请公布号 JPH03267816(A) 申请公布日期 1991.11.28
申请号 JP19900065915 申请日期 1990.03.16
申请人 OKI ELECTRIC IND CO LTD 发明人 TANOI SATOSHI
分类号 H03K17/16;G06F17/50;H03K17/687;H03K19/0175 主分类号 H03K17/16
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