| 摘要 |
PURPOSE:To obtain code data at high speed as the result of synthesizing images by parallelly operating the first and second extending circuits with a compressing circuit. CONSTITUTION:In respect to a first extending circuit 1, a wait control circuit 4 makes an output stop signal 3a 'L' until the image becomes a coordinate (bx,ay) and when the image exceeds the coordinate, the signal is made 'H'. In respect to a second extending circuit 2, an output stop signal 103b is made 'L' until the number of the output images becomes (bx-ax+1) and when the number exceeds the (bx-ax+1), the output stop signal 103b is made 'H'. Then, the output stop signal 103a is made 'L' and a select control signal 104 is made 'H' so that an output image 101a of the first extending circuit 1 can be inputted to a reducing circuit 5 again. Afterwards, this operation is repeated until the Y coordinate of the synthesized image exceeds the coordinate by and when the Y coordinate exceeds the coordinate by, the select control signal 104 is fixed to be 'H'. Thus, the code data can be obtained at high speed as the result of synthesizing images. |
