| 摘要 |
<p>A semiconductor memory circuit in which data are stored in a plurality of dynamic type memory cells located at cross points between bit lines and word lines, and in which the above-mentioned memory cells are refreshed at intervals of a predetermined time by a sense amplifier in order to hold the stored data. A first switching transistor is connected between first and second sense nodes of the sense amplifier, and a second switching transistor is connected between a second bit line and the second sense node. Further, a third switching transistor is connected between a bit line voltage source for precharging the first and second bit lines up to a predetermined voltage, and the first bit line, and a fourth switching transistor is connected between the second bit line and the bit line voltage source. <IMAGE></p> |
