| 摘要 |
<p>A data transfer controlling device (12:13) of a direct memory access controller (DMAC) type includes a transfer number data storage (131), a transfer number updating decrementer (130), a data setter (132) for setting predetermined initial data in the transfer number data storage (131), a terminal counter (121) with a decrementer (120) or an area counter (171) with a decrementer (170), a memory address register (141), an address updating section (140), and a DMA execution control section (100). The number of times of transfer for the subsequent DMA transfer is automatically set when the number of DMA transfers to be successively executed in response to each DMA transfer request has been completed. Immediately thereafter, the DMA transfer is repeated in response to the subsequent DMA transfer request. When the DMA transfer has bean completed to the final data in the DMA transfer source region of a memory, it is placed in an inhibited state. Thus, DMAC can respond to the DMA transfer request issued from a peripheral device at a high speed. <IMAGE></p> |
