| 摘要 |
Disclosed here are D-type flipflops cascaded in a semicustom LSI such as a standard cell or a gate array. Clock signals supplied to each of the flipflops have phases different from each other due to clock skew. A signal indicative of a data signal holding in the flipflop in one stage is applied to the flipflop in the preceding stage. The flipflop in the preceding stage is responsive to the applied signal for allowing a data signal held in a master latch to be transmitted to a slave latch. As a result, the passing through of data which might be possibly caused by the clock skew can be prevented. In other words, the passing of a data signal through two flipflops during one clock cycle can be prevented. <IMAGE> |
