| 摘要 |
<p>The present invention relates to an equalizing system in which an input signal is supplied to a series circuit of a plurality of delay means (D1, D2,...,Dm), the input signal and delayed output signals of the respective delay means (D1,D2,...,Dm) are multiplied with coefficient in coefficient multiplying (M0,M1,M2,...Mm) and multiplied outputs are added in adding means (A1,A2,...Am) to thereby produce an equalized output signal. In this equalizing system, the input signal is supplied to the series circuit of the plurality of delay means (D1,D2,...Dm) so that the input signal is transmitted in the positive direction within the series circuit so as to be sequentially delayed, the input signal is then transmitted in the reverse direction within the series circuit so as to be sequentially delayed, the input signal is transmitted again in the positive direction within the series circuit so as to be sequentially delayed, an amplitude error of the output equalized signal is detected in an error estimating unit (44), and coefficients multiplied with the delayed output signals of the respective delay (D1,D2,...Dm) are calculated in response to the detected amplitude error so that the amplitude error is minimized. <IMAGE></p> |
