发明名称 MULTILAYER WIRING BOARD
摘要 PURPOSE:To delay the propagation time of a signal by connecting viaholes and improve packaging efficiency on the surface layer of a board by providing a plurality of viaholes with intervals narrower than a standard grid pitch. CONSTITUTION:A plurality of viaholes 4 are provided with intervals narrower than a standard grid pitch P and further, they are connected mutually by a surface layer pattern 2 and an internal layer pattern 3. When it is required to delay the propagation time of a signal circulated to the pattern 2, disconnection of the pattern 2 permits the signal to circulate to a delay line 5 that is formed by the viaholes 4 connected to the pattern 3. Signal circulation through the line 5 connected by the viaholes 4, therefore, makes it possible to contrive the delay in the propagation time of the signal. This eliminates the need for mounting solid parts and installing wiring materials to a conventional board and further, the delay line 5 is formed without occupying the mounting space of the board 1. The packaging density in the board 1 is thus improved.
申请公布号 JPH03265191(A) 申请公布日期 1991.11.26
申请号 JP19900065111 申请日期 1990.03.15
申请人 FUJITSU LTD 发明人 YAMAMOTO TAKESHI
分类号 H05K3/46 主分类号 H05K3/46
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