发明名称 PRICISION 50% DUTY CYCLE CONTROLLER
摘要 Precision 50% Duty Cycle Controller A sine wave locked in phase and frequency to a carrier having a high second harmonic content, carrying information on the magnitude of a parameter, is applied to an open loop operational amplifier which provides a trapezoidal waveform to a high speed, differential transistor pair which provides a pair of squarewave signals whose duty cycles are regulated by varying the threshold at which the differential pair switches. The squarewaves may be used as a second-harmonic-free demodulating signal. The fundamental premise is that if the amplitude levels of the squarewave are known to a high degree of accuracy, and they are equal in the positive and negative directions, then the average value is zero only for a 50% duty cycle. A current regulator generates a selected current to a constant value with a high gain amplifier. This current is switched from one side to the other of the differential pair by the trapezoidal waveform. The voltage excursions may be controlled in equal amounts above and below zero by selecting the resistive values in the collector circuits of the differential pair to be of a magnitude which will accomplish that end. The average value of the resulting squarewave is regulated to zero by integrating the voltage at the output of one of the collectors of the differential pair and varying the threshold at the base of the other transistor to obtain a 50% duty cycle.
申请公布号 CA1292523(C) 申请公布日期 1991.11.26
申请号 CA19890610749 申请日期 1989.09.08
申请人 UNITED TECHNOLOGIES CORPORATION 发明人 FARINA, JOSEPH P.
分类号 G01C19/72;H03K5/04;H03K5/08;H03K5/156 主分类号 G01C19/72
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