发明名称 DOUBLE BUFFER CONTROL CIRCUIT
摘要 PURPOSE:To output an alarm signal notifying the generation of a slip in a prescribed timing by allowing a slip control means to control plane switching forcibly in a timing other than the timing of plane switching by means of a switching signal generating means. CONSTITUTION:A timing signal synchronizing with the plane switching operation at the data readout of a double buffer memory is inputted to a slip control means 131. When the timing signal and a frame pulse outputted from a phase shifting means 111 reach a prescribed phase relation, the forced plane switching is instructed. Then an alarm signal to inform the plane switching is fed to a switching signal generating means 121 and an alarm collecting section. Thus, an alarm signal informing the production of a slip is outputted in a prescribed timing.
申请公布号 JPH03265321(A) 申请公布日期 1991.11.26
申请号 JP19900064611 申请日期 1990.03.15
申请人 FUJITSU LTD 发明人 KAWAI YOSHIO
分类号 H04J3/06;G06F5/16;H04L7/08 主分类号 H04J3/06
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