| 摘要 |
PURPOSE:To reduce the time required for synchronization while keeping high accuracy by using a triangle wave as a control voltage to drive a VCO(Voltage Controlled Oscillator) circuit, and using a voltage when a rate of a change in a phase comparison output at that time is zero as the initial value of control voltage to the VCO circuit to activate a PLL circuit. CONSTITUTION:A rate of change zero detection means 12 detects a time of a rate of change in the output of difference between a frequency division output of the oscillated frequency of a VCO circuit 16 and an external clock frequency is almost zero. When the output of a rate of change zero detection frequency is generated, it is fed to a storage means 14 and a signal level of a triangle wave generating means 13 outputted from a selection means 15 is stored to the storage means 14. A control voltage generating means 11 sets the output of a signal level stored in the storage means 14 as an initial value to start the synchronization. Thus, accurate synchronization is reached in a short time. |
