| 摘要 |
A bus control system includes a handshake control circuit connected to receive an information transfer request signal from a data bus and to generate an information receipt acknowledge signal. The handshake control circuit operates to control a handshake between the information transfer request signal and the information receipt acknowledge signal. A first in-first out type memory is coupled to the data bus and is controlled by the handshake control circuit so as to receive information from the data bus and to output information to the data bus. In addition, the memory outputs an empty signal when the memory is empty, and the empty signal is supplied to the handshake control circuit. A counter is provided to be preset with an information transfer number and coupled to receive the information receipt acknowledge signal generated by the handshake control circuit so as to count the number of the information transfers executed and to generate a transfer completion ready signal when the information transfers of the number less than the preset number of the information transfer by one have been executed. Furthermore, an information receipt acknowledge hold control circuit is coupled to receive the transfer completion ready signal. The information receipt acknowledge hold control circuit operates to control the handshake control circuit, after the transfer completion ready signal is activated, so as to cause the handshake control circuit to hold the information receipt acknowledge signal in an active condition after the information receipt acknowledge signal in correspondence to a last information transfer is activated and until the empty signal is activated to indicate the emptiness of the memory.
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