| 摘要 |
PURPOSE:To attain high speed operation by extracting an output of n-set of flip-flops of a shift register as a parallel data in a timing given by a frequency division output from a frequency divider circuit. CONSTITUTION:An initial value of a 1st logic level is set to m-set of consecutive flip-flops less than the number (n) at the reset of each flip-flop and an initial value of a 2nd logic level different from the 1st logic level is set to remaining (n-m) sets of consecutive flip-flops. Then a frequency divider circuit 10 generates a frequency division waveform (output clock) whose frequency is 1/n to an input clock frequency given to each flip-flop 1-i (i=1,2,...,n) and whose duty factor is m/nX100%. That is, a serial input data with an input frequency is shifted-in sequentially to a flip-flop 6-i of a shift register 60 and outputs of the n-set of flip-flops 6-i of the shift register 60 are extracted as parallel data in a timing given by a frequency division output from the frequency divider circuit 10. Thus, high speed operation is attained. |
