| 摘要 |
<p>PURPOSE:To eliminate deviation at synchronization period and to prevent malfunction by giving and receiving an output of a 1st flip-flop between reception modules, ANDing all outputs at an AND gate for each reception module and receiving the output at a 2nd flip-flop by using a clock signal. CONSTITUTION:When a synchronizing signal from a transmission module 1 is received by plural reception modules 2, 3, outputs of 1st flip-flops 7, 8 in each reception module are received and given mutually and outputs of all the reception modules are ANDed by an AND gate in each reception module. Moreover, an output of each AND gate is received by 2nd flip-flops 9, 10 respectively by using a clock signal. Thus, even when a time to be set to the 1st flip-flops 7, 8 is deviated, the 2nd flip-flops 9, 10 are set simultaneously. Thus, deviation of a period of synchronization is avoided and malfunction is prevented.</p> |
