| 摘要 |
<p>This invention relates to a linear feedback sequence detector, such as for detecting ML sequence (maximum length shift register sequence), such as for use in decryption of encrypted data. A method of synchronising to a bit stream is provided, comprising the steps of: receiving a short sequence of bits which form part of a long cyclical sequence of bits; loading the short sequence of bits into a first register (10) having feedback means for counting through the long sequence when clocked; receiving at least one further bit of the long sequence from a predetermined location in the bit stream; performing a first test (14, 20) on the newly received bit to determine whether it is correctly received; performing a second test (20) on the newly received bit to determine whether it can reliably be corrected in view of subsequently received bits; using the resultant bit for updating a second register (18) having feedback means for counting through the long sequence when clocked if either of the first and second tests is successful; but clocking the second register (18) to generate the predicted equivalent of the at least one bit of said long sequence if said bit is determined as incorrectly received and cannot reliably be corrected, whereby the second register maintains its existing synchronisation with the bit stream. <IMAGE></p> |
