| 摘要 |
<p>This invention relates to apparatus for detecting a synchronisation sequence of data bits in a bit stream, where the sequence forms part of a cyclical linear feed back sequence. The apparatus may, for example, be used for frame synchronisation. It comprises: a first linear feedback circuit (11) for predicting the next received data bit and checking whether it is predicted correctly, a second linear feedback circuit (14) for generating the same second sequence, and thereby also predicting the next received data bit; means (13, 16) for setting the second circuit to the same position in the sequence as the first circuit when a first predetermined number of bits (N) has been received as predicted by the first circuit, and periodically thereafter when a new bit is received as predicted by the first circuit; means (18) for determining when a second predetermined number (M) of bits has been received as predicted by the second circuit, and means (16) for ceasing setting of the second circuit at that time, whereby the second circuit is locked to continue generating the sequence of bits to which it is set. <IMAGE></p> |
