发明名称 EXCEPTION HANDLING CIRCUIT
摘要 PURPOSE:To correct error with a microprogram even in the case of error in an instruction decoding circuit by indicating the address, which is generated from an instruction code and an exception code in software, to a wrong exception code detection memory and storing a correct exception code as contents of the address. CONSTITUTION:An instruction fetch register 1 which reads out an instruction in software from a storage circuit and holds this instruction, and an instruction decoding circuit 2 which decodes the instruction in the instruction fetch register 1 and generates the exception code indicating which specifications the instruction violates in the case of the violation of specifications are provided. A wrong exception code detection memory 3 is provided which takes the instruction held in the instruction fetch register 1 and the exception code as the address to output stored contents. Thus, the microprogram of exception handling is easily corrected even n the case of error (bug) in hardware.
申请公布号 JPH03262039(A) 申请公布日期 1991.11.21
申请号 JP19900061375 申请日期 1990.03.12
申请人 NEC CORP 发明人 OWADA TATSUO
分类号 G06F9/30;G06F11/00 主分类号 G06F9/30
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