摘要 |
<p>PURPOSE:To preclude the fear of writing an erroneous data by providing a clock generating means generating a clock to each unit. CONSTITUTION:Each of units 1, 2,..., N is provided respectively with clock supply sources 1H, 2H,..., NH and when a data is sent from the unit 1 to the unit N, the sender side unit 1 sends a reception timing pulse signal Nf-R to a reception memory MB-R of the unit . together with a data 1e. The unit N receives the transmission data, and control circuit NA uses a received clock signal 1a as a reception timing pulse signal Nf-R on the other hand, the reception timing pulse signal Nf-R sets the reception memory NB-R to store the data. Thus, normal data transmission is attained regardless of a transmission delay between units and the fear of write of an erroneous data is precluded.</p> |