发明名称 CIRCUIT AND METHOD FOR DETECTING PEAK
摘要 PURPOSE:To make improvement in operation margin by previously detecting the time difference between a positive polarity pulse and a negative polarity pulse and varying the delay time of the pulse of the one polarity in correspondence to this time difference. CONSTITUTION:A 1st pulser 5 which generates the pulse E of a prescribed pulse width at the rising edge of the positive polarity output pulse C of a compa rator 4 and a 2nd pulser 6 which generates the pulse D of a prescribed pulse width at the rising edge of the positive polarity output pulse K of the compara tor 4 are provided. A 1st delay circuit 7 which delays the output pulse E of the pulser 5 by the specified time, a 2nd delay circuit 8 which delays the output pulse D of the pulser 6 by the delay time determined by a control signal H, and an OR circuit 9 which ORs the output pulses F, G of the delay circuits 7, 8 are provided. Further, a ROM 10 which is controlled by a head address signal I and a means for delivering the output signal of the ROM 10 as the control signal H toward the delay circuit 8 are provided to constitute the above circuit. The operation margin at the time of data reproduction is improved in this way.
申请公布号 JPH03259405(A) 申请公布日期 1991.11.19
申请号 JP19900057025 申请日期 1990.03.07
申请人 NEC CORP 发明人 KIKUCHI KAZUO
分类号 G11B5/09;H03K5/153;H03K5/1532 主分类号 G11B5/09
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