| 摘要 |
<p>PURPOSE:To recognize a start-stop data speed automatically by adopting the constitution such that a bit serial character SD sent from an opposite equipment is converted into a parallel data and the converted data is compared with a predetermined reference value. CONSTITUTION:A counter 12 starts counting of a 9.6kHz clock. A shift register 13A converts the input character SD into a parallel data sequentially by using the clock as a shift clock. when four bits in the middle are inverted and the resulting data is inputted to an identification circuit 14A, an output of a flip-flop 15A goes to 8 to inform the detection of a code 21H. When a Q output of the flip-flop 15A goes to 'H', the signal is fed back to in OR gate G2 to close the gate. In this case, since an output of an identification circuit 14B detecting a frequency of 600ps is not the code 21H, the output remains at 'L' as shown in (k) and a Q output of a flip-flop 15B similarly remains at 'L'.</p> |
