| 摘要 |
PURPOSE:To reduce the number of circuit elements by transforming a polarity amplitude display input from amplitude attribute display to the complementary display of 2 and obtaining the result of multiplying two inputs by the complementary display of 2. CONSTITUTION:In order to transform the polarity amplitude expression to the complementary expression of 2, it is enough to exclusively OR X3 as MSB and a bit excepting for the MSB and to add the X3. Out of signals 21 of X input terminals X3-X0, signals X2-X0 excepting for the MSB and the X3 are exclusively ORed by logic gates 22-24 and outputs A2-A0 are obtained. Further, by adding the signal X3 to a carry input Ci of an M cell 32 as the M cell of the least significant bit to obtain the partial product of a multiplier, the signal of the polarity amplitude display can be transformed to the signal in the display of 2. Thus, since multiplication can be executed by the complementary display of 2 in a multiplier part 25 using Booth algorithm with X3 and A2-A0 as X inputs and Y3-Y0 as Y inputs, the number of circuit elements can be reduced. |
