发明名称 AIS TRANSMISSION CIRCUIT
摘要 PURPOSE:To use other clock to send an AIS signal when a PLL circuit of a channel has a fault by connecting a read clock of each channel at a receiver side in parallel with a selector of each channel at a low-order group of an asynchronous digital multiplexer. CONSTITUTION:Receiver side read clocks 121-124 for each channel selected by selectors 21-24 are respectively inputted to receiver buffer memories 31-34. The selectors 21-24 are subject to selection control by receiver side read signal interrupt signals 131134. Thus, an AIS(Alarm Indication Signal) signal is sent by using a read clock of other PLL circuit when any of PLL circuits 11-14 has a fault in a channel through the provision of the selectors 21-24 connecting in parallel with each channel of outputs of the PLL circuits 11-14 of each channel of a receiver side of a low order.
申请公布号 JPH03258046(A) 申请公布日期 1991.11.18
申请号 JP19900054993 申请日期 1990.03.08
申请人 NEC CORP;NEC MIYAGI LTD 发明人 SAKAMOTO MITSURU;OKUMURA JUNJI
分类号 H04J3/14;H04L7/033 主分类号 H04J3/14
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