| 摘要 |
PURPOSE:To reduce the bit synchronization extraction time by selecting a bit synchronization extraction system or a DPLL system depending on the frame synchronization. CONSTITUTION:When no frame synchronization is detected from a frame synchronization detection means 6, a change point detection means 5 presets a counter means 2 at a change point of a reception data to extract bit synchronization. When the frame synchronization detection means 6 detects frame synchronization, a pulse number of a self-running signal is increased/decreased in response to the phase difference obtained at the output of a phase comparison means 3. Thus, the bit synchronization extraction time is reduced by selecting the bit synchronization extraction system depending on the frame synchronization. |
