发明名称 SLIP DETECTION CIRCUIT
摘要 <p>PURPOSE:To prevent the erroneous detection of clock slip by counting the cycles of first and second clocks by using a third clock with high frequency, and comparing those two counting results with each other. CONSTITUTION:The third clock is a clock to count the cycles of the first and second clocks, respectively, and is provided with the frequency higher than that of the first and second clocks. The cycle of the first clock can be counted by a first counter means 111 and that of the second clock by a second counter means 121 by performing a counting operation synchronized with the third clock. A comparison means 131 compares the two counting results with each other, and a comparison result is outputted as the detection result of the clock slip. In such a manner, it is possible to detect the clock slip in spite of the phase stats of the first and second clocks, and to prevent the clock slip detected erroneously.</p>
申请公布号 JPH03256421(A) 申请公布日期 1991.11.15
申请号 JP19900056178 申请日期 1990.03.06
申请人 FUJITSU LTD 发明人 FUJIOKA YASUSHI
分类号 H04J3/06;G06F1/04;H04L7/00 主分类号 H04J3/06
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