摘要 |
<p>A metal silicide layer (82) in or on a body of silicon wafer (10) is used for interconnecting two or more CMOS circuit devices (50, 52). In addition to a polysilicon layer (42, 44, 46) and a metal layer (96), the metal silicide layer (82) provides an additional layer of local interconnect which can be performed at high density to reduce the size of the die while including the same number of circuit devices. An amorphous silicon layer (64) doped at selected regions (72a-72b, 72c-72d, 74a-74b) is used to connect the silicide layer to the source and drain regions of the devices (50, 52).</p> |