| 摘要 |
PURPOSE:To prevent the superposition of an error by providing plural latches, and fixing data by one of the latches and outputting data from the other multistage latches in response to a clock. CONSTITUTION:The output of an inverter IR 8 is connected to the input of the IR 12 through a transmission gate 10, and the output of the IR 12 is connected to the input of the IR 13, and the output of the IR 13 is connected to an output terminal 14, and a latch circuit is constituted. Besides, the output of the IR 13 is fed back to the input of the IR 12 through the transmission gate 11. In the preceding stage of the latch circuit, the latch circuit operating at the same timing and of the same configuration is provided, and when the clock phiA contained in a non-superposed two-phase clock is given, it responds to its trailing edge, and fixes the read data. Next, when the clock phiB is impressed to the latch circuit of the above-mentioned poststage, the fixed data is outputted from the output terminal 14. Then, the hold period of the fixed data becomes longer, and the temporal allowance of a data changed point and an input data fixed point becomes larger. Thus, even if the latch circuits are connected into a multistage, the error can be prevented from being superposed. |
