| 摘要 |
PURPOSE:To prevent the increase of machine cycle and to execute the data processing at high speed by predicting carry of a low order adding means. CONSTITUTION:The adding circuit is provided with two operand registers 1 - 4, two adding means 5, 6 for executing addition between high order data and addition between low order data and a carry holding means 7, a carry inverting means 13, a carry comparing means 8, an initial value generating means 9 for generating an initial value of the carry holding means 7, a carry selecting means 10 for selecting an input of the carry holding means 7, and an output means 14. In such a state, in the case of adding the high order data, addition can be executed by one clock cycle in the most cases by predicting carry from the low order nate data. In such a way, the increase of a machine cycle is prevented, and the performance of a data processing comes to high speed. |
