发明名称 FRAME SIGNAL GENERATOR
摘要 PURPOSE:To reduce a memory capacity required to generate a frame signal by reading a start point address and an end point address or the start point address and a data length on a scanning line from a frame information memory so as to generate the frame signal. CONSTITUTION:A vertical start point detection circuit 15 and a vertical end point detection circuit 16 of a frame signal generating circuit 14 compare an output of a vertical counter 12 with a readout data from a frame information memory 11 to detect a start point and an end point in the vertical direction to which a reduced picture is inserted. Moreover, a horizontal start point detection circuit 17 and a horizontal end point detection circuit 18 of the frame signal generating circuit 14 compare an output of a horizontal counter 13 with a readout data from the frame information memory 11 to detect a start point and an end point in the horizontal direction to which a reduced picture is inserted. As a result, the frame signal to insert a reduced picture signal is generated. Thus, the memory quantity required to generate the frame signal is reduced.
申请公布号 JPH03254287(A) 申请公布日期 1991.11.13
申请号 JP19900051312 申请日期 1990.03.02
申请人 FUJITSU LTD 发明人 NAGAOKE TAKAO
分类号 H04N5/265;G06T1/00;G06T3/00;G09G5/12;G09G5/36;H04N1/387;H04N5/275 主分类号 H04N5/265
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