发明名称 Digital to analog converter with switching logic minimization
摘要 A plurality of resistors are connected between a source terminal to which a reference voltage is applied and a grounded terminal. A plurality of switches, which constitute a first switch group and derives voltages divided by the resistors, are respectively connected to the odd-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. A plurality of switches, which constitute a second switch group and derives voltages divided by the resistors, are respectively connected to the even-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. Each of the switches of the first and second switch groups is connected to a logical circuit serving as a decoder for selecting one of the switches in accordance with the content of bits other than the least significant bit of an input digital signal. The first and second switch groups are connected to a third switch group which selects the first or second switch in accordance with the content of the least significant bit of the digital signal.
申请公布号 US5065159(A) 申请公布日期 1991.11.12
申请号 US19900604241 申请日期 1990.10.29
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KUWANA, KIYOHISA
分类号 H03M1/68;H03M1/76 主分类号 H03M1/68
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