| 摘要 |
PURPOSE:To reduce the total number of clock transmission lines by arranging plural clock selection parts on the outside of plural logical processing parts and in the vicinity of clock generation parts, and distributing clock signals to respective logical processing parts. CONSTITUTION:A clock generation part 41 applies n clock signals CK1 to CKn to a clock selection part 42 through n clock transmission line A1 to An. Each of respective clock selector circuits 421 to 42m selects any one of clock signals CK1 to CKn based upon a selection command signal applied from a selection command signal generation circuit 43 and outputs the selected signal. A data processing part 50 has m logical processing parts 51 to 5m and clock signals outputted from respective clock selector circuits 421 to 42m are applied to the corresponding logical processing parts 51 to 5m through clock feeding lines B1 to Bm. Thus, the number of clock transmission lines can be reduced. |
