| 摘要 |
<p>PURPOSE:To set up the writing and reading phases of the elastic storage circuit (ES) to optimum states in the initial state by providing the ES with a variable length shift register circuit for delaying input data and a frame signal. CONSTITUTION:The value of a counter circuit 27 indicates a difference between a frame signal position with a twice period and the 1st reading bit of the ES 17 and is stored in a latch circuit 28 and the output of the circuit 28 is applied as an address for a variable length shift register 29 for delaying input data and a variable length shift register 30 for delaying the frame position signal with the twice period. A pattern generator 19 is reset by the output of the register 30 and the writing timing of ESs 17, 18 is determined by a 2-frequency dividing circuit 3, an EXOR gate 4 and AND gates 5, 6. Thus, the writing and reading phases of the elastic storage circuit can be set up to the optimum states in the initial state.</p> |
