| 摘要 |
A clock signal producing circuit for a data storing and reproducing system in which a reference clock signal having a predetermined frequency is generated, a first sync-signal detection signal is generated when the time between two adjacent pulses in the input signal which is measured by the reference clock signal becomes equal to the predetermined reference value, the clock edge pulse is separated from the input signal using the first sync-signal detection signal and then outputted, and a reproducing clock signal having a predetermined frequency coinciding with the generating timing of the separated clock edge pulse is generated.
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