| 摘要 |
A zero-phase restart circuit that provides a new circuit element in the path of the incoming data signal in order to delay the data signal by an amount equal to the delay caused by the restart circuitry. This ensures that the phase difference between the two signals will be zero at restart and thus effectively cancels out the residual error seen with the prior art. This technique remains effective well into higher data rates. The advantages of the present invention allows the circuit to operate near its limit without suffering large transients on the VCO control voltage and the VCO frequency. The overall system will not be limited by the transient response on the VCO control voltage nor the VCO frequency. It allows for higher operating speeds of data. Further, the new method will allow the system to better tolerate the jitter of the incoming data such that the restrictions on the jitter performance of the incoming data can be reduced substantially, i.e., allow more jitter to exist on the data.
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