| 摘要 |
PURPOSE:To reduce current due to a clock signal to prevent the generation of noise by successively turning on and of switching elements by control clocks outputted from a ring counter. CONSTITUTION:In accordance with the counting off clock signals CLK synchronized with data DIN, output signals C1 to C6 are successively outputted from the ring counter CTR. A transistor(TR) Q1 is turned on by the output C1 and the 1st bit D1 of the data is stored in a latch circuit L1. Similarly, respective bits are stored in latch circuits L2 to L6. When the output C1 is obtained again, the data stored in the circuit L2 are outputted through a TR Q2 and data D7 are stored in the circuit L1. Thus, input data are delayed by 5 bits of the signal CLK and outputted by repeating the operation and the 5-bit shift register can be obtained. |
