| 摘要 |
PURPOSE:To prevent the fraction part from becoming undefined data by controlling an output data switching part by an output switching signal, setting the part before the fraction part of output data as an output of a parallel-series conversion shift register, and setting the fraction part as specific data being an output of a data generating part. CONSTITUTION:The processor is provided with a data generating part 11 for generating specific data, and an output data switching part 12 for switching and outputting output data of a parallel-series converting part 35 and output data of the data generating circuit 11, and an output switching signal generating part 13. In such a state, by the timing for outputting the final one piece or plural pieces of input series data corresponding to a fraction portion at the time when the number of input series data of one group is divided by the number of converting stages of a series-parallel converting part 31, the output data switching part 12 outputs an output of the data generating part 11. Also, by the timing for outputting the input series data before the fraction, the output data switching part 12 outputs an output of the parallel-series converting part 35. In such a way, even in the case a fraction exists in input data, it can be prevented that the data of the fraction part becomes an undefined state at the time of output. |
