| 摘要 |
PURPOSE:To avoid an error of frequency information due to overlapped timing of counter reset by generating frequency information without resetting a counter for each period of count when a recovered clock is counted. CONSTITUTION:A result of count of a sampling clock at a counter 4 is read by registers 6, 7 by using a 27.8Hz clock outputted from a frequency divider 5 and when a subtractor 8 subtracts a content of the register 6 from the content of the register 7, the count of a sampling clock counted at a period of 1/27. 8sec is obtained and it is outputted as frequency information. In this case, the value is nearly 5.2X10<5> and 19-bits are required in binary notation and since only + or -114 of fluctuation as frequency information exists from the assumption of + or -200ppm in the sampling clock fluctuation range and + or -20ppm in the fluctuation range of the transmission line clock, it is not required to send all of 19 bits as the frequency information and only low-order 8-bit has only to be sent. Thus, an error due to reset timing is eliminated. |
