| 摘要 |
PURPOSE:To obtain an output clock pulse having an optional duty by providing an exclusive OR circuit receiving a frequency division clock pulse and a delayed frequency division clock pulse and setting properly the delay of a delay circuit. CONSTITUTION:A frequency division circuit 11 divides a received input clock pulse A whose period is T into two and outputs a frequency division clock pulse D. An exclusive OR circuit 12 exclusively ORs the pulse D and a delayed frequency division clock pulse E resulting from retarding the pulse D by a delay 8 at a delay circuit 13, then the duty of an H level of an output clock pulse R is 100% delta/T%. The delay delta of the delay circuit 13 is varied optionally in a range of 0<=delta<T. Thus, the duty of the output clock pulse R is set optionally independently of the duty of the input clock pulse A. |
