| 摘要 |
A device for digital signal processing and particularly suited for video and image processing applications. The device includes a linear array of 1024 processing elements (PE's), an external controller interface, input/output ports, and an external memory interface. The input/output ports allow the device to interface to equipment such as digitizing cameras and video display monitors. The device uses a single instruction multiple data topology (SIMD) and incorporates two modes of communication: horizontal and vertical. Shift registers provide horizontal, i.e. parallel, communication between the PE's in the linear array. The linear array of processing elements provides one PE for each digital sample, e.g. a pixel, thereby allowing a sequence of data samples, e.g. a video line, to be processed in real-time. Each PE includes a bit-serial arithmetic logic unit, a cache memory and an external memory interface. All communication within a PE is along a one-bit wide bus, i.e. vertical mode, using a single move instruction with variable source and destination addresses. The processing capability of the device is further enhanced by having a serial-parallel multiplier in each PE. For applications requiring more than 1024 PE's, two or more devices can be cascaded together. In another embodiment of the present invention, dual-port memories provide horizontal communication between the PE's in the linear array.
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