| 摘要 |
<p>The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy (18) plane and a 'through-via' plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials (13, 19). The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.</p> |
